日本电子维修技术 2915 11年1286

PPVOUT_S0_LCDBKLT  pin 38-40 (upper left of  J9000),  D9701 (upper right of  TBT Host);PP3V3_SW_LCD  L9000 (upper left  of  T4001);LCD_PWR_EN  pin 1 (lower left)  of  U9000 (6 pin , left of  T4001) or pin 1 (down) of  R9094 (left of U9000), XP25-5  output;LVDS_DDC_CLK/DATA  pin 2 (near J9000) of  R9011/R9010 (near pin 6/7 of  J9000); connect to B1，B2 and B3，B4 pin of U9270 (SN74LV4066A,LVDS DDC MUX,Muxed Graphics Support), and pull up to PP3V3_S0 through 100K R9010 and R9011。 Input come from DG & PCH, select is XP25 output;LVDS_EG_DDC_CLK  pull up to PP3V3_S0GPU through 20K pin 2 (right) of  R9270 [left of pin 1 (lower left) of  U9270 (lower right of  51125, 14 pin)]LVDS_EG_DDC_DATA  pin 2 (down) of  R9271 (right of  U9270);PPVOUT_SW_LCDBKLT_FB  test point on the upper left of  J5650 (left FAN CONN);BKL_PWM  pin 1 (left) of  C9704 [the first component with down to up on the right of  U9701 (BKLT driver)] and test point on the left of  this pin, 25-5 output;BKL_EN  pin 2 (left) of  R9715 & R9731 (the second & third compoment with up to down on the right of  U9701) and test point on the left of them;FB_B1_VREFD2  pin 2 (left) of  R8584 [the first resistor with up to down on the right of  U8550 (Frame Buffer)], the volt of this node to be 0.9V from 1.05V indicate ran passed DG and then will display;PPVCORE_S0_AXG  pin 1 (down) of  C1737 [big capacitor, no stuff, upper right of  J2500 (PROCESSOR MINI XDP)] down to 0.4V from 0.6V indicate ran passed IG ;LVDS_CONN_B_CLK_F_N/P  pin 2(left) of  R9242/R9240 (the third/fourth resistor with up to down on the left of XP25-5),  or  L9011 (back of  J9000) and pin 29/30 of  J9000;  LVDS_CONN_A_CLK_F_N/P  pin 2 (left) of  R9222/R9220 (the sixth/fifth resistor with down to up on the left of  XP25-5), or  L9010 (under pin 17/18 of  J9000);LVDS_EG_A_CLK_P/N  R9660 [the second risistor (stuff level) with right to left on the upper right of  XP25-5];GMUX_RESET_L  receives  PLT_RESET_L  through pin 2 (right) of  R2887 [the middle one on the left of  U2880 (5 pin and on the upper left of  CS4206)]；PEX_CLKREQ_L  is  Whistler  output to XP25-5  through 0Ω R8795 (the stuff vertical one on the middle left of  U8900 (GPUVCORE REG)；PEG_CLKREQ_L  is XP25-5 output to PCH and pull up to  PP3V3_S0  through 10K R1846;PP1V2_S0  &  GMUX_TOE  R9640 (the third resistor with right to left under  XP25-5);PP3V3_S0  &  GMUX_CFG0  R9645 (the fifth resistor with right to left under  XP25-5);PP1V8_S0_GMUX_R  all the pins of those four components near  Q9706 (6 pin and lower right of TBT host);FB_RESET_L  R8262 [the second component with right to left of stuff level under  U8550 (Frame buffer on the rightmost)];EG_RESET_L  pin 1 (left) of  R9691 (the fifth component with down to up on the right of  XP25-5);GPU_CLK100M  GPU_CLK27M  R8730  R8731 {402, double on the upper left of  U8700 [10 pin, GPU Reference Clocks, on the left of  Y8700 (GPU OSC 27M, back side of  DG)]},near the two screw holes;GPU_OSC_27M_XTALIN  upper left of  Y8700;PM_ALL_GPU_PGOOD  pin 2 (up) of  R9990 (the second component with left ot right above  J5100 & keyboard CONN);file:///C:\Users\S\AppData\Local\Temp\ksohtml\wpsB7F8.tmp.jpg EG_PWRSEQ_EN  pull up to PP3V3_S0 through 1K pin 1 (down) of  R9684 [a lonely stuff vertical 201 resistor on the lower left of  C7252 (the big capacitor stuff vertical on the upper left of south bridge)]；MEM ODT  non test point, is  pin 116 & 120;MEM_RESET_L  pin 2 of  R3217 (down pin) & R3216 (up pin) [lower left of screw hole ZT0984 on the upper right of  J2900 (down DIMM, board back side)]  or pin 3 (lower right) of  Q3215 (6 pin);LPC_AD<0,1,3,2>  R1860/1/3/2  the seventh/eighth/ninth/tenth component with up to down on the left of  PCH;LPC_FRAME_L  R1864 (the 14 component with up to down on the left of  PCH);LPCPLUS_RESET_L  &  PLT_RESET_L  R2881 [stuff level above  J5100 (no stuff) and keyboard CONN];SMC_LRESET_L  sources by  PLT_RESET_L  through  R2883 ;PLT_RST_CPU_BUF_L  pin 4 of  U2890 (5 pin and left of  CS4206),pull up to 1.05V, input is  PLT_RESET_L;PLT_RST_BUF_L  pin 4 of  U2880 (5 pin and on the upper left of  CS4206);PM_THRMTRIP_L  pull up to  PP1V05 through  R1104 (stuff vertical one on the left of  C1641 (the second with the column 4 big capacitors on the upper right of  J2900 (down DIMM)], CPU to PCH;LPC_PWRDWN_L  test point above the first resistor with right to left of the row components on the right of  BIOS,  SUS_STAT  pin of  PCH output;PM_PCH_SYS_PWROK  R9962 {the first one with right to left under  U9950 [PCH S0 PWRGD, 8 pin and above keyboard CONN and  J5100 (no stuff)]}, include  SMC_DELAYED_PWRGD, CPUIMVP_PGOOD  &  ALL_SYS_PWRGD;CPUIMVP_PGOOD  pin 2 (up) of  R9950 (left of  R9962);CPUIMVP_TON  pin 1 (up) of  R7402 (the rightmost one of those four components on the lower right of 95831);CPU_VIDALERT_L  R1310 (the fourth component with up to down on the left of  CPU);CPU_VIDSCLK/OUT  R7479/R7480 [two resistors on the upper left of 95831 (IMVP REG)];SPI_MLB_CS_L  pin 1 (upper left) of  U6100 (BIOS);CPUIMVP_VR_ON  pin 1 (lower right of  95831) sources by  ALL_SYS_PWRGD  through  R7974 (left of  R7402);CPU_PWRGD  R2140 (the first resistor with down to up on the right of  PCH), is PCH send to  UNCOREPWRGOOD pin of  CPU, PROCPWRGD pin of  PCH output;DMI_CLK100M_CPU_N  point on the lower left of  C1643 [the down on of the column 4 big capacitors on the upper right of  J2900 (down DIMM)];LPC_CLK33M_SMC  R2855 (the sixth component with left to right above PCH);LPC_CLK33M_GMUX  R2857 (the third component with right to left on the upper left of  PCH), PCH output;SYSCLK_CLK25M_SB  pin 9 (upper right) of  U2800 (32k &25M);PM_MEM_PWRGD  pin 6 (upper left) of  Q3220 (6 pin , lower left of  PCH);PP1V5_S3RS0_CPUDDR  pin 1,2,3 (lower right) of  Q7801 [8 pin and on the middle above J2900 (down DIMM)];PWROK  &  APWROK  receives  PM_PCH_PWROK  sources by  SMC_DELAYED_PWRGD  through  R9960 (upper right of  U9950);ALL_SYS_PWRGD  pin 4 (right) of  Q7950 (S0 Rail PGOOD, on the left of  MIC CONN);PPVCCSA_S0_REG  L7010 (left of  J3100 (up DIMM)];PM_PECI_PWRGD  come from  CPUVCCIOS0_PGOOD  through  R7975 (outside on the lower right of  95831), send to  IO;PCH CORE VCC & VCCASW  sources by  PP1V05_S0  = PPCPUVCCIO_S0_REG  L7630 [stuff vertical above  J3100 (up DIMM)] ;SLP_LAN  pin of  PCH  GPIO29_SLP_LAN_L  pull up  to  PP3V3_SUS through  R1982 [upper right of  J5713 (KB CONN)];SMC_PBUS_VSENSE  R5303 {upper right of  Q7080 [Inrush Limiter, between TPad CONN & battery CONN)]}, EN is  PM_SLP_S3_R_L;PM_SLP_S3_R_L  pin 1 of  Q7865 [3 pin, lower right of  J3401 (WIFI CONN)];PPDDR_S3  L7330 (upper right of  up DIMM);P1V5CPU_EN  pin 2 & 3 (right) of  U7801 (right of  Q7801,8 pin too), sources by  PM_SLP_S4_L  through  R3205;PM_SLP_S4_L  pin 1 (left) of  R3205 (stuff level on the upper right of down DIMM and left of two 6 pin chips);PM_SLP_S5_L  pin 1 (left) of  R7922 [upper left of  Q7820 (3V3_SUS FET, 6 pin) and upper right of keyboard CONN], PCH to IO direct;SMC_CLK32K  test point on the right of  L6995 (3V42);PM_RSMRST_L  pin 1 (lower left) of  U7930 {6 pin and between  BAT CONN &  U2600 [40 pin, USB HUB1 (left one)]} output , PP3V3_SUS*PP3V3_S5  create ;PM_BATLOW_L  pin 2 of  Q5040 (3 pin and upper right of keyboard CONN  J5713,pin 1 is  PP3V3_SUS);PP3V3_SUS  down 4 pin of  Q7820 (6 pin on the upper right of  keyboard CONN);PP5V_SUS  down 4 pin of  Q7840 (upper right Q7820 and 6 pin);PM_SUS_EN  pin 2 (left)  of  R7917 (stuff level and no stuff, right of  Q7820), come from and gate  U7940 (PM_SLP_SUS_L & SMC_BATLOW_L);PM_SLP_SUS_L  pin 1 (right) of  R7917;PM_DSW_PWRGD  pin 1 (right) of  R1909 [the second resistor with up to down from  C1802 (a biger capacitor in the middle of the column components on the left of  PCH]S5_PWRGD  pin 2 (right) of  R7941 (outside one on the lower left of  51980);VCCDSW3_3  =  PP3V3_S5  pin 1,2,3 (upper right) of  Q7830 (8 pin and on the upper right of  J5713);P3V3S5_EN  &  SMC_PM_G2_EN  R7940 (the fourth component with right to left under pin 21 of  51980);PCH_DSWVRMEN  pull up to  PPVRTC_G3H through pin 2 (right) of  R1915 (the second component with down to up on the left and near PCH);RTC_RESET_L  &  PPVRTC_G3H  pin 1 (right) of  C2810 [under pin 1 (lower left) of  U2800 (16 pin, left of  PCH)];SMC_ONOFF_L  R5016 (upper left of  J5713)  and  R5015 [upper left of  U5010 (8 pin, under PCH)];SMC_RESET_L  pin 5 (upper left of  U5010);SMC_EXTAL/XTAL  Y5010 above  IO;PP3V3_S5_AVREF_SMC  pin 8 (lower left) of  U5010;SMC_DCIN_VSENSE  R5313 [the first one with right to left above  J5800 (IPD Flex Connector, Internal Pad)], come from  Q5310, EN is  SMC_BC_ACOK;SMC_BC_ACOK  pin 14 (upper left) of  6259  or  pin 1 & 2 of  U6901 [the smaller 5 pin above  U5701 (PSOC USB CONTROLLER)];SMC_DCIN_ISENSE  &  CHGR_AMON  R5441 [the first one with up to down on the lower left of  L6995 (3V42)]; SMC_LID  R6961 (the second component with left to right under MIC CONN), pull up to 3V42;file:///C:\Users\S\AppData\Local\Temp\ksohtml\wpsB80A.tmp.jpg G3_POWERON_L  only pull up to pin 1 (up) of  R5072 (the second component with left to right of the outside row under  IO);PP3V42_G3H  L6995 (upper right of battery CONN);U6990  above  L6995,  R6995 (on the left of  U6990, connect pin 7,4 & 3 of U6990),  D6990  on the left of  L6995;


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楼主这是从哪里转来的东西，乱乱的，，，

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天书！！！！

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这是来刷分来的，建议禁言


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哪里复制的 全是英文……


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什么的东西啊

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根本看不懂啊，几乎看不明白啥

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信号在每段的开头，倒过来的时序。慢慢看，会懂的。

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好吧， 我就慢慢看下吧，反正没事

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应该大致的时序还是对的。另外不是转来的，我自己写的

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辛辛苦苦写的哦。刷得了多少分嘛。不懂就闭嘴。如果让你这样的或当网站管理员……

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自己写的。哪里有得复制啊？你找来我看看。

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不是复制的，自己写的。里面有很多的语法错误，所以没有别人这样写的。你是版主，见多识广，有见过写成这样的资料吗？

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给点耐心研究研究就懂了。别说天书啊，我写的但我不是天哪。

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苹果一个板子的时序。

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是啊，你自己都说哪里有这样的资料。如果写时序，你写成这样估计没有人会看吧，本来很乱的你写出来更乱，还用英文，还用自己都不知道的语法……在显摆吗？大家都在维修行业混。没有必要吧，还有要写时序的话你看看各位版主的写的，简单明了，你也可以标注脚位，但你不是说你什么就不说，直接一堆英文信号，没有题目，没有序号，没有人会单独研究你到底发的是什么，所以请楼主修改下，不然后面再来的还是看不懂

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学一下英文很有裨益的。如果你看不懂可以研究，你看不懂的东西多了去了，对于你看不懂的，你就骂或者认为是显摆吗？那你只能一辈子做维修了。我是乱写的，但你是否知道我花了很多时间精力的。我用英文是希望找到知音，没办法取悦所有人。

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那就接着找吧……

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Good brother. How many times do you want to write? The professional data we can get is still very limited. So it's hard for us to do a lot of research.

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写得不错，还标明了位置。但是觉得时序有点错，例如：cpu_pwrgd应该在cpu_imvp_vr_on后面吧。而且bios第一只叫在待机的时候就已经有3.3v了，而你把它写在开机后。是不是有点不对啊 电路 电子 维修 我现在把定影部分拆出来了。想换下滚，因为卡纸。但是我发现灯管挡住了。拆不了。不会拆。论坛里的高手拆解过吗？ 评论 认真看，认真瞧。果然有收 电路 电子 维修 求创维42c08RD电路图 评论 电视的图纸很少见 评论 电视的图纸很少见 评论 创维的图纸你要说 版号，不然无能为力 评论 板号5800-p42ALM-0050 168P-P42CLM-01
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